Accessing / Sampling the DUT signals using specman elite e-language

Specman elite e-language supports in driving or sampling
-> VHDL signals at any hierarchy level
-> Verilog registers and wires at any hierarchy level.
In order to access the DUT we need to use single quotes with '~' to denote top-level module name.
'~/instance HDL path /signal name‘
Ex:
‘~/top_tb/data_in’
Here the top_tb refers to the Top HDL module name and data_in refers to the signal name present in the top_tb module.
-> To Drive a Value from Specman elite e-language to DUT, apply the following mechanism.
‘~/top_tb/reset’ = 1;
-> To Sample a DUT value to Specman elite Variables ( Struct / Unit) , apply the following mechanism.
Packet_u.data_out = ‘~/top_tb/data_out”;