Temporal Checker mainly depends on the Temporal Expressions ( TE's) and these are directed statments ( one line statement) with major reference to Reference clocks.
For ex :
I have shown a small example which expects certain event to be emitter based on the following conditions.
<'
unit bus_u {
event bus_clk is change('clk') @sim;
event transmit_start is rise('transcation_done') @bus_clk;
event transmit_end is rise('transmit_done') @bus_clk;
event bus_cycle_length;
on transmit_start {
out ("found the transmit_start event...", sys.time);
};
expect bus_cycle_length is @transmit_start => {[0..9];@transmit_end} @bus_clk
else dut_error("Bus cycle did not end in 10 cycles");
};
extend sys {
bus : bus_u is instance; keep bus.hdl_path() == "top";
};
'>
Showing posts with label e-verification. Show all posts
Showing posts with label e-verification. Show all posts
Monday, June 7, 2010
Wednesday, March 18, 2009
How to extend methods in e-language
Specman e-language has the built in features to extend the predefined and
user-defined methods in order to have new contents.
The extension can be done in the same file where the original method is declared or in another new file.
Specman e-language supports the following features for extending the methods
a) is first => which means add before the existing e code
b) is also => which means add after the existing e code
c) is only => which means override/replace the existing e code
user-defined methods in order to have new contents.
The extension can be done in the same file where the original method is declared or in another new file.
Specman e-language supports the following features for extending the methods
a) is first => which means add before the existing e code
b) is also => which means add after the existing e code
c) is only => which means override/replace the existing e code
Wednesday, March 11, 2009
How to write an e-program block
The e program block is indicated by the keyword struct.
The Program Block contains the following format.
struct struct_name {
--- Field declaration;
--- Methods with /without return type;
};
The main e-Program block is where:
· Fields are declared inside the struct_name
· Variables are declared inside the methods
· Executable statements are carried out
· Calls to methods with arguments are made
The Program Block contains the following format.
struct struct_name {
--- Field declaration;
--- Methods with /without return type;
};
The main e-Program block is where:
· Fields are declared inside the struct_name
· Variables are declared inside the methods
· Executable statements are carried out
· Calls to methods with arguments are made
Tuesday, March 10, 2009
Basic syntax of e-language
Specman e-language is case sensitive in nature for both the predefined syntax keywords and user-defined names.
The name my_struct_s and my_STRUCT_S are both different structs defined in the e-language.
struct my_struct_s {
--- Action to be performed
}
struct my_STRUCT_S {
---- Action to be performed
}
Here struct is a specman e-language keyword.
The important aspect of the e-language is that the e-code written should be within the delimiters (e.g <' '>) and the code written outside the delimiters are considered as comments. In order to have single inline comments within the delimiters we can have both the VHDL / Verilog format ( e.g -- or // ) .
Ex :
The below code shows a sample e-language code structure
<'
struct my_packet_s {
// Field Declaration ( single line comment)
Addr : byte;
Data : byte;
Len : uint (bits:6);
method_name() is {
--- Action required
}
}; // end of struct my_packet_s
'>
The name my_struct_s and my_STRUCT_S are both different structs defined in the e-language.
struct my_struct_s {
--- Action to be performed
}
struct my_STRUCT_S {
---- Action to be performed
}
Here struct is a specman e-language keyword.
The important aspect of the e-language is that the e-code written should be within the delimiters (e.g <' '>) and the code written outside the delimiters are considered as comments. In order to have single inline comments within the delimiters we can have both the VHDL / Verilog format ( e.g -- or // ) .
Ex :
The below code shows a sample e-language code structure
<'
struct my_packet_s {
// Field Declaration ( single line comment)
Addr : byte;
Data : byte;
Len : uint (bits:6);
method_name() is {
--- Action required
}
}; // end of struct my_packet_s
'>
Monday, March 9, 2009
Introduction to specman e-language
Specman e verification language is an HVL (Hardware Verification Language) Language and an IEEE standard language used by most of the verification engineers for Block/SOC Verification. It is one of most advanced language in terms of methodology and technology for building the Verification environment.
Specman e-language has a unique concept called Aspect-oriented Programming, that enables easier reuse and provide "extendibility" features for derivative environments and follows the eRM Methodology.
According to the eRM (e Reusable Methodology) the Verification environment is designed to have a Stimulus Generator, Driver, BFM (Bus Functional Module) and to intergrate all these elements it has an Agent which could be Transmitter (Tx) or Receiver (RX).
The Top Verification Environment categories into Active and Passive Elements. The Active Elements consists of Stimulus Generator, Driver and BFM whereas the Passive Elements Consists of Monitors (e.g Checkers, Signal Map and Functional Coverage). These Elements can be Enabled / Disabled by built in switch depending on the requirement. The Functional Coverage is one of the important element in the Specman e-verification which gives the verification engineer to cover all the important functionality in terms of coverage elements.
Specman e-language has a unique concept called Aspect-oriented Programming, that enables easier reuse and provide "extendibility" features for derivative environments and follows the eRM Methodology.
According to the eRM (e Reusable Methodology) the Verification environment is designed to have a Stimulus Generator, Driver, BFM (Bus Functional Module) and to intergrate all these elements it has an Agent which could be Transmitter (Tx) or Receiver (RX).
The Top Verification Environment categories into Active and Passive Elements. The Active Elements consists of Stimulus Generator, Driver and BFM whereas the Passive Elements Consists of Monitors (e.g Checkers, Signal Map and Functional Coverage). These Elements can be Enabled / Disabled by built in switch depending on the requirement. The Functional Coverage is one of the important element in the Specman e-verification which gives the verification engineer to cover all the important functionality in terms of coverage elements.
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